Advancements in the miniaturization of semiconductor devices continue to emphasize the importance of structural integrities of semiconductor devices. Similarly, advancements in the manufacture of semiconductor devices continue to emphasize the importance of efficiencies of the rate and cost of fabrication, particularly with increasing complexities of manufacturing smaller and smaller semiconductor devices. Manufacturers desire high yield, minimized costs, and reliable semiconductor devices for testing and both installation for and function of use.
Increased complexities of etching patterns, such as for matrix patterns for vias under pads, and etching loading effects causing differences of etching rates for different shapes (e.g., skinny rectangles compared to squares) and sizes (large and small) for etching must be taken into account. By way of example, the layout of a conventional via under a pad, such as for testing or mounting the semiconductor device, is a matrix pattern with equal spacing and identical sizing, thus reducing loading effect, but decreasing the etching rate. FIG. 1 is an example of such a conventional via under a pad with an equally sized and equally spaced density matrix pattern.
A common problem with conventional matrix pattern vias under metal pads is inter-metal dielectric (IMD) fatigue and cracking, which can result from wafer sorting testing, wire bonding testing, or installation wire bonding, thereby causing damage to the integrated circuit (IC). For example, a probe or bonding ball may poke through the metal pad and/or crush or crack the IMD. A matrix pattern via may not be strong enough to withstand such forces. Thus, the semiconductor device may be damaged at and/or around the pad by such physical contact of wire bonding or probing.
Accordingly, there remains a need in the art for improved methods to increase via etching rate and avoiding inter-metal dielectric cracking and damage to the integrated circuit.